View ADP31810001C_2078365.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

5-bit or 6-bit programmable 2-,3-,4-phase synchronous buck controller adp3181 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features selectable 2-, 3 - or 4-phase op eration at up t o 1 mhz per phase 14.5 m v wors t-case mv diffe rential sensing error over temperature logic-level pw m outputs for i n terface to ext e rnal high power drivers active current balancing between all outp ut phases built-in power good/cr owbar bl anking supports on-the-fly vid co de chan ges digitally programmable outp ut can be switc h ed between vrm 9 (5 -bit) a n d vrd 10 ( 6 -b it) vid co des programmable short-circuit protection with programmable latch-off dela y applic ati o ns desktop pc power supplies fo r: next-generatio n intel ? proces sors vrm mo dules general description the ad p3181 is a hig h l y ef f i cien t m u l t i p has e s y n c hr on o u s b u ck - s w i tc h i ng re g u l a tor c o n t rol l e r opt i mi z e d for c o n v e r t i ng a 1 2 v mai n su pply in to t h e c o re su p p ly vol t ag e re qu ire d b y hig h p e r f o r ma n c e i n t e l p r o c e s s o rs. i t us es a n in t e r n al 6-b i t d a c t o r e ad a vol t a g e iden tif i ca tio n (vid) c o de dir e c t l y f r o m t h e p r o c e s s o r , w h ich is us e d t o s e t t h e ou t p u t v o l t a g e . the cpuid in p u t s e le c t s w h et h e r t h e d a c co des ma t c h t h e vrm 9 o r vrd 10 sp e c if ic a t io ns. i t us es a m u l t i m o d e p w m a r chi t e c t u r e t o dr i v e t h e log i c-le v e l o u t p u t s a t a p r og ra mma b l e sw i t ch in g f r e q u e n c y t h a t can b e o p t i mi ze d fo r vr si ze and ef f i cien c y . the phas e r e l a t i on shi p o f t h e o u t p ut sig n als ca n b e pro g r a m m e d to prov i d e 2 - , 3 - , or 4 - ph a s e op e r a t i o n , allo w i n g f o r th e co n s tr ucti o n o f u p t o f o ur co m p le m e n t a r y bu c k - s w i t c h i n g s t a g e s . the ad p3181 a l s o in c l udes p r og ra mma b l e n o -l o a d o f fs et a nd sl op e f u nc t i ons to a d j u st t h e output vo lt ag e a s a f u nc t i o n of t h e lo ad c u r r en t s o tha t i t is al wa ys o p timal l y p o si tio n e d f o r a sys t em tran sien t. th e adp3181 p r o v ides acc u ra t e and r e l i a b le shor t - c i rc u i t pr ote c t i on , a d j u st abl e c u r r e n t l i m i t i n g , a n d a del a ye d p o w e r go o d o u t p u t t h a t acco m m o d a t es o n -t h e -f ly o u t p ut v o l t a g e cha n g e s r e q u es t e d b y t h e cpu . the de v i ce is sp e c if ie d o v er t h e co mm er cial t e m p er a t ur e ra n g e o f 0c t o +85c a nd is a v a i lab l e in a 28 -lead t s so p p a c k a g e . func tio n a l block di agram 19 11 12 15 10 28 13 14 26 8 25 24 23 17 18 22 21 20 16 12 3 4 5 76 9 27 v cc gnd adp3181 en delay ilimit pwrgd rt rampadj pwm2 fb pwm3 pwm4 sw1 cssum cscomp sw2 sw3 sw4 csref pwm1 vid4 vid3 vid2 vid1 vid0 fbrtn cpuid comp precision reference soft start uvlo shutdown and bias oscillator vid dac dac + 300mv dac ? 250mv csref en current- limiting circuit current- balancing circuit delay crowbar current limit cmp cmp cmp cmp 2-/3-/4-phase driver logic en set reset reset reset reset 04796-0-001 fi g u r e 1 .
adp3181 rev. 0 | page 2 of 24 table of contents specifications ..................................................................................... 3 te s t c i rc u it s ....................................................................................... 5 absolute maximum ratings ............................................................ 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ........................................................................ 9 start-up sequence ......................................................................... 9 master clock frequency ............................................................ 10 output voltage differential sensing ........................................ 10 output current sensing ............................................................ 11 active impedance control mode ............................................. 11 current control mode and thermal balance ....................... 11 volt age c ont rol mo de ................................................................ 11 soft start ...................................................................................... 12 current limit, short-circuit, and latch-off protection ....... 12 dynamic vid .............................................................................. 13 power good monitoring ........................................................... 13 output crowbar ......................................................................... 13 output enable and uvlo ........................................................ 13 application information ................................................................ 15 setting the clock frequency ..................................................... 15 soft-start and current-limit latch-off delay times ........... 15 inductor selection ...................................................................... 15 designing an inductor ............................................................... 16 output droop resistance .......................................................... 16 inductor dcr temperature correction ................................. 17 output offset .............................................................................. 17 c out selection ............................................................................... 17 power mosfets ........................................................................ 18 ramp resistor selection ............................................................ 19 current limit setpoint .............................................................. 20 feedback loop compensation design .................................... 20 c in selection and input current di/dt reduction .................. 21 building a switchable vr9/vr10 design ............................... 22 layout and component placement ............................................. 23 general recommendations ....................................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 5/04revision 0: initial version
adp3181 rev. 0 | page 3 of 24 specifications vcc = 12 v, fbrtn = gnd, t a = 0c to +85c, unless otherwise noted. 1 table 1. parameter symbol conditions min typ max unit error amplifier output voltage range 2 v comp 0.7 3.1 v accuracy v fb relative to nominal dac output, referenced to fbrtn, cssum = cscomp. see figure 2. ? 14.5 +14.5 mv line regulation ? v fb vcc = 10 v to 14 v 0.05 % input bias current i fb 14 15.5 17 a fbrtn current i fbrtn 100 140 a output current i o(err) fb forced to v out C 3% 500 a gain bandwidth product gbw (err) comp = fb 20 mhz slew rate c comp = 10 pf 25 v/ s vid inputs input low voltage v il(vid) cpuid > 4.5 v 0.8 v cpuid < 4.0 v 0.4 v input high voltage v ih(vid) cpuid > 4.5 v 2.0 v cpuid < 4.0 v 0.8 v input current i vid vid(x) = 0 v, cpuid > 4.5 v 40 70 a vid(x) = 0 v, cpuid < 4.0 v 20 35 a pull-up resistance r vid 40 60 k ? internal pull-up voltage cpuid > 4.5 v 2.25 2.5 2.75 v cpuid < 4.0 v 1.1 1.25 1.4 v vid transition delay time 2 vid code change to fb change 400 ns no cpu detection turn-off delay time 2 vid code change to 11111 to pwm going low 400 ns cpuid input input low voltage v il(cpuid) 0.4 v input high voltage v ih(cpuid) 0.8 4.0 v vr 9 detection threshold voltage 4.0 4.5 v input current i cpuid cpuid = 0 v 20 3.5 a pull-up resistance r cpuid 4.0 60 k ? oscillator frequency range 2 f osc 0.25 4 mhz frequency variation f phase t a = 25c, r t = 250 k ? , 4-phase 155 200 245 khz t a = 25c, r t = 115 k ? , 4-phase 400 khz t a = 25c, r t = 75 k ? , 4-phase 600 khz output voltage v rt r t = 100 k ? to gnd 1.9 2.0 2.1 v rampadj output voltage v rampadj rampadj C fb ? 50 +50 mv rampadj input current range i rampadj 0 100 a current sense amplifier offset voltage v os(csa) cssum C csref. see figure 3. ? 3 +3 mv input bias current i bias(cssum) ? 50 +50 na gain bandwidth product gbw (csa) 10 mhz slew rate c cscomp = 10 pf 10 v/ s input common-mode range cssum and csref 0 2.7 v positioning accuracy ? v fb see figure 4. ? 77 ? 80 ? 83 mv output voltage range 0.05 2.7 v output current i cscomp 500 a
adp3181 rev. 0 | page 4 of 24 parameter symbol conditions min typ max unit current balance circuit common-mode range v sw(x)cm ? 600 +200 mv input resistance r sw(x) sw(x) = 0 v 20 30 40 k ? input current i sw(x) sw(x) = 0 v 4 7 10 a input current matching ? i sw(x) sw(x) = 0 v ? 5 +5 % current limit comparator output voltage normal mode v ilimit(nm) en > 0.8 v, r ilimit = 250 k ? 2.9 3 3.1 v in shutdown v ilimit(sd) en < 0.4 v, i ilimit = ?100 a 400 mv output current, normal mode i ilimit(nm) en > 0.8 v, r ilimit = 250 k ? 12 a maximum output current 2 60 a current limit threshold voltage v cl v csref C v cscomp , r ilimit = 250 k ? 105 125 145 mv current limit setting ratio v cl /i ilimit 10.4 mv/ a delay normal mode voltage v delay(nm) r delay = 250 k ? 2.9 3 3.1 v delay overcurrent threshold v delay(oc) r delay = 250 k ? 1.7 1.8 1.9 v latch-off delay time t delay r delay = 250 k ? , c delay = 12 nf 1.5 ms soft start output current, soft-start mode i delay(ss) during start-up, delay < 2.4 v 15 20 25 a soft-start delay time t delay(ss) r delay = 250 k ? , c delay = 12 nf, vid code = 011111 1 ms enable input input low voltage v il(en) 0.4 v input high voltage v ih(en) 0.8 v input current, input voltage low i il(en) en = 0 v ? 1 1 a input current, input voltage high i ih(en) en = 1.25 v 10 25 a power good comparator undervoltage threshold v pwrgd(uv) relative to nominal dac output ? 180 ? 250 ? 320 mv overvoltage threshold v pwrgd(ov) relative to nominal dac output 230 300 370 mv output low voltage v ol(pwrgd) i pwrgd(sink) = 4 ma 225 400 mv power good delay time during soft start 2 r delay = 250 k ? , c delay = 12 nf, vid code = 011111 1 ms vid code changing 100 250 s vid code static 200 ns crowbar trip point v crowbar relative to nominal dac output 230 300 370 mv crowbar reset point rela tive to fbrtn 630 700 770 mv crowbar delay time t crowbar overvoltage to pwm going low vid code changing 100 250 s vid code static 400 ns pwm outputs output low voltage v ol(pwm) i pwm(sink) = ? 400 a 160 500 mv output high voltage v oh(pwm) i pwm(source) = 400 a 4.0 5 v supply dc supply current 5 10 ma uvlo threshold voltage v uvlo vcc rising 6.5 6.9 7.3 v uvlo hysteresis 0.7 0.9 1.1 v 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not tested in production.
adp3181 rev. 0 | page 5 of 2 4 test circuits 12v 1.25v 100nf adp3181 1 2 3 28 27 26 4 8 10 12 14 5 6 7 21 24 23 22 9 11 17 18 19 13 15 16 20 25 5 -bit code 12nf vid4 vid3 vid2 vid1 vid0 cpuid fbrtn fb comp en pwrgd delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 cscomp gnd cssum csref ilimit 1k ? 250k ? 20k ? 250k ? 100nf 1 f + 04796-0-004 f i gure 2. closed-l oop o u tput v o ltage a c cur a c y 04796-0-005 cssum 18 cscomp 17 28 vcc csref 16 gnd 19 39k ? 100nf 1k ? 1.0v adp3181 12v v os = cscomp? 1 v 40 f i gure 3. cu rrent s e ns e a m pl ifi e r v os 04796-0-006 cssum 18 cscomp 17 28 vcc csref 16 comp 8 fb 9 gnd 19 200k ? 10k ? 200k ? 1.0v adp3181 ? v 12v ? v fb = fb ? v = 80mv ? fb ? v = 0mv 100nf f i gure 4 . p o si tio n in g v o l t a g e
adp3181 rev. 0 | page 6 of 2 4 absolute maximum ratings table 2. parameter rating vcc ? 0.3 v to +15 v fbrtn ? 0.3 v to +0.3 v vid0 to vi d4, cpuid, en, delay, ilimi t , cscomp, rt, p w m1 to pw m4, comp ? 0.3 v to +5.5 v sw1 to sw4 ? 5 v to +25 v all other inputs and outputs ? 0.3 v to vcc + 0 .3 v storage temperature ? 65c to +150c operating ambient temperature range 0c to 85c operating juncti on temperature 125c thermal imped ance ( ja ) 1 0 0 c / w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . a b s o lute m a x i m u m r a t i ng s a pply i n d i v i du a l ly on ly , not i n co m b in a t ion. u n less o t h e r w is e sp e c if ie d a l l o t her v o l t a g es a r e re f e re nc e d to g n d . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adp3181 rev. 0 | page 7 of 2 4 pin conf iguration and fu nction descriptions 04796-0-011 adp3181 top view (not to scale) vid4 1 vcc 28 vid3 2 pwm1 27 vid2 3 pwm2 26 vid1 4 pwm3 25 vid0 5 pwm4 24 cpuid 6 sw1 23 fbrtn 7 sw2 22 fb 8 sw3 21 comp 9 sw4 20 pwrgd 10 gnd 19 en 11 cscomp 18 delay 12 cssum 17 rt 13 csref 16 rampadj 14 ilimit 15 f i gure 5. pin config ur ation table 3. pin fu nction descriptions pin o. ae description 1 to 5 vid4 to vi d0 voltage identificati on dac inputs. these five pi ns are pulled up to an internal reference, providing a logic 1 if left open. when in normal mode, the da c output pro g rams the fb re gulation voltag e based on the conditio n of the cpuid pin (see t a ble 4 and t a bl e 5). leaving vid4 through vid0 open results in the adp3181 going into a no cpu mo de, shutting off its pwm ou t p uts. 6 cpuid cpu dac code selection input. when this pin is pulled > 4.5 v, the internal dac read s its inputs based on the vr 9 vid tab l e (see table 4). when this pin is < 4 v, the dac r e ads its inputs based on the vr 10 vid table (see table 5) and treats cp uid as the vid5 input. 7 fbrtn feedback return. vid dac and error amplifier r e ference for re mote sensi n g of the output volt age. 8 fb feedback input. error amplifier i n put for remote se nsing of the output voltage. a n ex ternal resist or between this pin and the outpu t volt age sets the no-lo a d offset point. 9 comp error amplifier outp ut and co mpensation point. 10 pwrgd power good output. open-drain output that si gnals when the output voltage is outside of the proper operating range . 11 en power supply enable input. pulling th is pin to gnd disables the pwm outpu t s. 12 delay soft-start delay and current lim i t latch-off delay setting input. an external re si stor and capac i tor connected between this pin and gnd sets the soft-s tart ramp-up time and the overcurrent latch- off delay time. 13 rt frequency setting resistor inpu t. an external resi stor connected between this pin and gnd sets the oscillator freque ncy of the device. 14 rampadj pwm ramp curr ent input. an external resi stor from the convert e r inp ut voltage to this pi n sets the internal pwm ramp. 15 ilimi t current limit se tpoint/enable output. an extern al resi stor from this pin to gnd sets the current limit threshold of the converter. this pin is active ly pulle d low when the adp3181 e n input is low, or when vcc is bel o w its uvlo thresho l d , to signal to the driver ic that the dri ver high-sid e an d low-sid e outp uts should go low. 16 csref current sense reference voltag e input. the voltage on this pin i s used as the reference for the c u rrent sense a m plifier and the power good and crow bar functi ons. this pin s h ould b e connected to the commo n point of the output inductors. 17 cssum current sense summing node. external resi stor s from each switch node to this pin sum the ave r age inductor currents together to measure the total output current. 18 cscomp current sense compen sation p o int. a resistor a n d capa citor from this pin to cssum determine the slope of the load line an d the positionin g loop res pon se time. 19 gnd ground. all internal biasing and the logic output signals of the device are refer e nced to this ground. 20 to 23 sw4 to sw1 current balance inputs. inputs for measuring th e current level i n each ph ase. t h e sw pins of unused phase s sh ould be left open. 24 to 27 pwm4 to p m w1 logic-level pwm outputs. eac h output is connected to the input of an external mosfet driver such as the adp3413 or ad p3418. connecting the pwm3 a n d/or pwm4 outputs to gnd ca uses th at phase to turn off, allowing the adp3181 to operate as a 2-, 3-, or 4-phase controlle r. 28 vcc supply voltage for the device.
adp3181 rev. 0 | page 8 of 2 4 typical perf orm ance cha r acte ristics 4 3 2 1 0 0 5 0 100 150 200 250 300 04796-0-002 r t value (k ? ) mas t e r clock fre q ue ncy (mhz) f i gure 6. m a ster cl ock f r equ e nc y v s . r t 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 04796-0-003 oscillator frequency (mhz) s u p p l y curre nt (ma) t a = 25 c 4-phase operation f i gure 7. su p p ly cu rr e n t v s . o s cil l a t o r f r equ e nc y
adp3181 rev. 0 | page 9 of 24 theory of operation the adp3181 combines a multimode, fixed-frequency pwm control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck cpu core supply power converters. the internal vid dac can be used in the intel 5-bit vrm 9 or 6-bit vrd/vrm 10 designs, depending on the setting of the cpuid pin. multiphase operation is important for producing the high currents and low voltages demanded by todays micro- processors. handling the high currents in a single-phase converter places high thermal demands on the components in the system such as the inductors and mosfets. the multimode control of the adp3181 ensures a stable, high performance topology for ? balancing currents and thermals between phases. ? high speed response at the lowest possible switching frequency and output decoupling. ? minimizing thermal switching losses due to lower frequency operation. ? tight load line regulation and accuracy. ? high current output from 4-phase operational design. ? reduced output ripple due to multiphase cancellation. ? pc board layout noise immunity. ? ease of use and design due to independent component selection. ? flexibility in operation for tailoring design to low cost or high performance. start-up sequence two functions are set during the start-up sequence: the number of active phases and the vid dac configuration. the number of operational phases and their phase relationship is determined by internal circuitry that monitors the pwm outputs. normally, the adp3181 operates as a 4-phase pwm controller. grounding the pwm4 pin programs 3-phase operation, and grounding the pwm3 and pwm4 pins programs 2-phase operation. when the adp3181 is enabled, the controller outputs a voltage on pwm3 and pwm4 that is approximately 675 mv. an internal comparator checks each pins voltage versus a threshold of 300 mv. if the pin is grounded, it is below the threshold and the phase is disabled. the output resistance of the pwm pin is approximately 5 k? during this detection time. any external pull-down resistance connected to the pwm pin should not be less than 25 k? to ensure proper operation. pwm1 and pwm2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. after this time, if the pwm output was not grounded, the 5 k? resistance is removed and it switches between 0 v and 5 v. if the pwm output was grounded, it remains off. the pwm outputs are logic-level devices intended for driving external gate drivers such as the adp3418. because each phase is monitored independently, operation approaching 100% duty cycle is possible. also, more than one output can be on at a time for overlapping phases. the vid dac configuration is determined by the voltage at the cpuid pin. if this pin is pulled up to > 4.5 v, the vid dac operates with five inputs and generates the vr 9 output voltage range as shown in table 4. if cpuid is < 4 v, the vid dac treats cpuid as the vid5 input of vr 10, and operates as a 6- bit dac using the output voltage range given in table 5. table 4. vr 9 vid codes for the adp3181, cpuid > 4.25 vid4 vid3 vid2 vid1 vid0 output 1 1 1 1 1 no cpu 1 1 1 1 0 1.100 v 1 1 1 0 1 1.125 v 1 1 1 0 0 1.150 v 1 1 0 1 1 1.175 v 1 1 0 1 0 1.200 v 1 1 0 0 1 1.225 v 1 1 0 0 0 1.250 v 1 0 1 1 1 1.275 v 1 0 1 1 0 1.300 v 1 0 1 0 1 1.325 v 1 0 1 0 0 1.350 v 1 0 0 1 1 1.375 v 1 0 0 1 0 1.400 v 1 0 0 0 1 1.425 v 1 0 0 0 0 1.450 v 0 1 1 1 1 1.475 v 0 1 1 1 0 1.500 v 0 1 1 0 1 1.525 v 0 1 1 0 0 1.550 v 0 1 0 1 1 1.575 v 0 1 0 1 0 1.600 v 0 1 0 0 1 1.625 v 0 1 0 0 0 1.650 v 0 0 1 1 1 1.675 v 0 0 1 1 0 1.700 v 0 0 1 0 1 1.725 v 0 0 1 0 0 1.750 v 0 0 0 1 1 1.775 v 0 0 0 1 0 1.800 v 0 0 0 0 1 1.825 v 0 0 0 0 0 1.850 v
adp3181 rev. 0 | page 10 of 24 table 5. vr 10 vid codes for the adp3181, cpuid used as a vid5 input vid4 vid3 vid2 vid1 vid0 cpuid output vid4 vid3 vid2 vid1 vid0 cpuid output 1 1 1 1 1 1 no cpu 1 1 0 1 0 0 1.2125 v 1 1 1 1 1 0 no cpu 1 1 0 0 1 1 1.2250 v 0 1 0 1 0 0 0.8375 v 1 1 0 0 1 0 1.2375 v 0 1 0 0 1 1 0.8500 v 1 1 0 0 0 1 1.2500 v 0 1 0 0 1 0 0.8625 v 1 1 0 0 0 0 1.2625 v 0 1 0 0 0 1 0.8750 v 1 0 1 1 1 1 1.2750 v 0 1 0 0 0 0 0.8875 v 1 0 1 1 1 0 1.2875 v 0 0 1 1 1 1 0.9000 v 1 0 1 1 0 1 1.3000 v 0 0 1 1 1 0 0.9125 v 1 0 1 1 0 0 1.3125 v 0 0 1 1 0 1 0.9250 v 1 0 1 0 1 1 1.3250 v 0 0 1 1 0 0 0.9375 v 1 0 1 0 1 0 1.3375 v 0 0 1 0 1 1 0.9500 v 1 0 1 0 0 1 1.3500 v 0 0 1 0 1 0 0.9625 v 1 0 1 0 0 0 1.3625 v 0 0 1 0 0 1 0.9750 v 1 0 0 1 1 1 1.3750 v 0 0 1 0 0 0 0.9875 v 1 0 0 1 1 0 1.3875 v 0 0 0 1 1 1 1.0000 v 1 0 0 1 0 1 1.4000 v 0 0 0 1 1 0 1.0125 v 1 0 0 1 0 0 1.4125 v 0 0 0 1 0 1 1.0250 v 1 0 0 0 1 1 1.4250 v 0 0 0 1 0 0 1.0375 v 1 0 0 0 1 0 1.4375 v 0 0 0 0 1 1 1.0500 v 1 0 0 0 0 1 1.4500 v 0 0 0 0 1 0 1.0625 v 1 0 0 0 0 0 1.4625 v 0 0 0 0 0 1 1.0750 v 0 1 1 1 1 1 1.4750 v 0 0 0 0 0 0 1.0875 v 0 1 1 1 1 0 1.4875 v 1 1 1 1 0 1 1.1000 v 0 1 1 1 0 1 1.5000 v 1 1 1 1 0 0 1.1125 v 0 1 1 1 0 0 1.5125 v 1 1 1 0 1 1 1.1250 v 0 1 1 0 1 1 1.5250 v 1 1 1 0 1 0 1.1375 v 0 1 1 0 1 0 1.5375 v 1 1 1 0 0 1 1.1500 v 0 1 1 0 0 1 1.5500 v 1 1 1 0 0 0 1.1625 v 0 1 1 0 0 0 1.5625 v 1 1 0 1 1 1 1.1750 v 0 1 0 1 1 1 1.5750 v 1 1 0 1 1 0 1.1875 v 0 1 0 1 1 0 1.5875 v 1 1 0 1 0 1 1.2000 v 0 1 0 1 0 1 1.6000 v master clock frequency the clock frequency of the adp3181 is set with an external resistor connected from the rt pin to ground. the frequency follows the graph in figure 6. to determine the frequency per phase, the clock is divided by the number of phases in use. if pwm4 is grounded, then divide the master clock by 3 for the frequency of the remaining phases. if pwm3 and 4 are grounded, divide by 2. if all phases are in use, divide by 4. output voltage differential sensing the adp3181 combines differential sensing with a high accuracy vid dac and reference and a low offset error amplifier to maintain a worst-case specification of 14.5 mv differential sensing error over its full operating output voltage and temperature ranges. the output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 100 a to allow accurate remote sensing. the internal error amplifier compares the output of the dac to the fb pin to regulate the output voltage.
adp3181 rev. 0 | page 11 of 24 output current sensing the adp3181 provides a dedicated current sense amplifier (csa) to monitor the total output current for proper voltage positioning versus load current and for current limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side mosfet. this amplifier can be configured several ways depending on the objectives of the system: ? output inductor esr sensing without a thermistor for lowest cost. ? output inductor esr sensing with a thermistor for improved accuracy with tracking of inductor temperature. ? sense resistors for highest accuracy measurements. the positive input of the csa is connected to the csref pin, which is connected to the output voltage. the inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, cssum. the feedback resistor between cscomp and cssum sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. the gain of the amplifier is programmable by adjusting the feedback resistor to set the load line re quired by the microprocessor. the current information is then given as the difference of csref C cscomp. this difference signal is used internally to offset the vid dac for voltage positioning and as a differential input for the current limit comparator. to provide the best accuracy for the sensing of current, the csa has been designed to have a low offset input voltage. also, the sensing gain is determined by external resistors so that it can be made extremely accurate. active impedance control mode for controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the cscomp pin can be scaled to equal the droop impedance of the regulator times the output current. this droop voltage is then used to set the input control voltage to the system. the droop voltage is subtracted from the dac reference input voltage directly to tell the error amplifier where the output voltage should be. this differs from previous implementations and allows enhanced feed-forward response. current control mode and thermal balance the adp3181 has individual inputs for each phase, which are used for monitoring the current in each phase. this information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. this current balance information is independent of the average output current information used for the positioning described previously. the magnitude of the internal ramp can be set to optimize the transient response of the system. it is also monitors the supply voltage for feed-forward control for changes in the supply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. detailed information about programming the ramp is given in the application information section. if desired, external resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase may have better cooling and can support higher currents. resistors rsw1 through rsw4 (see the typical application circuit in figure 10) can be used for adjusting thermal balance. it is best to have the ability to add these resistors during the initial design, so make sure placeholders are provided in the layout. to increase the current in any phase, make r sw for that phase larger (make r sw = 0 for the hottest phase; do not change during balancing). increasing r sw to only 500 ? makes a substantial increase in phase current. increase each r sw value by small amounts to achieve balance, starting with the coolest phase first. voltage control mode a high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. the control input voltage to the positive input is set via the vid logic. this voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with a resistor, rb, and is used for sensing and controlling the output voltage at this point. a current source from the fb pin flowing through rb is used for setting the no-load offset voltage from the vid voltage. the no-load voltage is negative with respect to the vid dac. the main loop compensation is incorporated in the feedback network between fb and comp.
adp3181 rev. 0 | page 12 of 24 soft start the p o w e r - on ra m p -u p t i m e o f t h e o u t p ut v o l t a g e is s e t w i t h a c a p a ci to r and r e sisto r in p a r a l l el f r o m t h e de l a y p i n to g r o u n d . th e r c time co n s ta n t a l s o det e r m in es t h e c u r r en t limi t la tch o f f t i me as ex pla i ne d in t h e fol l o w in g s e c t i o n. i n uvlo o r when e n is a log i c lo w , th e d e l a y p i n is h e l d a t g r o u nd . af t e r t h e uvlo t h r e sh old is r e ach e d a nd en is a lo g i c hig h , t h e d e l a y c a p a ci to r is cha r ge d w i t h a n i n ter n a l 20 a c u r r en t s o ur ce . the o u t p u t v o l t a g e fol l o w s t h e ram p in g v o l t a g e on t h e d e la y p i n , li mi ti n g t h e i n - r us h curr e n t . th e s o ft - s ta r t tim e dep e n d s on t h e va l u e o f vid d a c a nd c dl y , w i t h a s e c o n d a r y ef fe c t f r o m r dl y . refer t o t h e a pplica t ion i n fo r m a t ion s e c t ion fo r det a i l e d infor m a t io n on s e t t i n g c dl y . i f ei th er e n is t a k e n lo w o r v c c dr o p s b e lo w uvl o , the d e la y ca p a ci to r is r e set t o gr o u n d t o b e r e ad y f o r a n o t h e r s o f t -s t a r t c y c l e . f i gur e 8 s h o w s th e typ i cal s t a r t-u p wa vef o r m s f o r th e ad p318 1. fi g u r e 8 . t y p i c a l s t a r t - u p w a v e f o r m s chann e l 1: pwr g d , chan nel 2: csr e f , chann e l 3: del a y , chann e l 4: c o m p current limit, short- circuit, an d latch- o f f p r ot ect i on the ad p3181 c o m p a r es a p r og ra mma b l e c u r r en t-limi t s e t p o i n t t o t h e v o l t a g e f r o m t h e o u t p u t of t h e c u r r en t s e n s e am plif ier . the le ve l o f c u rr en t limi t is s e t wi t h t h e r e sis t o r f r o m t h e ilimit p i n t o g r o u n d . dur i n g n o r m al o p er a t io n, th e v o l t a g e o n ilimit is 3 v . th e c u r r en t thr o ug h the ext e r n al r e sis t o r is in t e r - nal l y s c aled t o g i v e a c u r r en t-limi t thr e sh old o f 10.4 mv/ a. i f t h e dif f er en ce i n v o l t a g e b e twe e n csref a nd csc o mp r i s e s a b o v e t h e c u r r en t-li mi t t h r e sh old , t h e i n t e r n al c u r r en t-limi t a m plif ier co n t rols t h e in t e r n a l c o mp v o l t a g e to ma in t a in t h e a v era g e ou t p u t c u r r en t a t t h e li mi t. af t e r t h e li mi t i s r e ach e d , t h e 3 v p u l l -u p o n t h e d e l a y p i n is dis c o n n e c t e d , and t h e ex ter n a l del a y c a p a ci to r i s dis c ha rge d th r o ugh th e e x t e rn al r e si s t o r . a co m p a r a t o r m o n i t o r s t h e d e l a y v o l t a g e a nd sh u t s o f f t h e co n t r o l l er w h e n t h e v o l t a g e dr o p s be lo w 1.8 v . the c u r r en t-limi t la t c h-o f f de l a y tim e is th us s e t b y th e r c tim e con s t a n t dis c ha rg in g f r o m 3 v t o 1.8 v . th e a p plica t ion i n fo r m a t io n s e c t ion dis c uss e s t h e s e le c t io n o f c dl y a nd r dl y . b e ca us e t h e co n t r o l l er co n t in ues t o c y cle t h e phas es d u r i n g t h e la t c h - o f f d e la y t i m e , i f th e sh o r t i s r e m o v e d be fo r e th e 1. 8 v t h re sho l d i s re a c he d, t h e c o n t ro l l e r re tu r n s to n o r m a l op e r a t i o n . the r e co v e r y ch a r ac t e r i s t ic dep e n d s on t h e s t a t e o f pwr g d . i f t h e o u t p ut v o l t ag e is w i t h i n t h e pwr g d wi n d o w , t h e co n t r o l l er r e sum e s n o r m a l o p era t ion. h o w e v e r , if sh o r t circ ui t has c a us e d t h e o u t p ut v o l t ag e t o dr o p b e lo w t h e pwr g d t h r e s h old , a s o f t - st a r t c y cle is ini t ia t e d . the l a t c h-o f f f u n c t i on can b e r e s e t ei t h er b y r e m o vi n g and r e a p p l yin g v c c t o th e ad p318 1, o r b y p u l l in g th e e n p i n lo w fo r a sh o r t t i m e . t o dis a b l e t h e sh o r t-cir c ui t la t c h-o f f f u n c t i on, t h e e x te r n a l re s i stor to g r ou nd s h ou l d b e l e f t o p e n , a n d a h i g h v a lu e ( > 1 m ? ) re s i stor shou l d b e c o n n e c te d f r om de l a y to v c c. this p r e v en ts t h e de l a y c a p a ci t o r f r o m dis c ha rg in g s o t h e 1.8 v t h r e sh old is ne ver r e ache d. th e r e sisto r ha s a n i m p a c t o n th e so f t - s t a r t tim e be ca us e th e curr e n t th r o ugh i t a d d s t o th e in t e r n al 20 a c u r r en t s o ur ce . f i gu r e 9 . o v er cu rr en t la t c h - o ff w a v e fo rm s chann e l 1: csref , chann e l 2: del a y , chann e l 3: c o m p , chann e l 4: p h as e 1 switch nod e dur i n g s t a r t-u p when t h e o u t p u t v o l t a g e is b e lo w 200 mv , a s e c o nd ar y c u r r en t l i m i t i s ac t i ve b e c a u s e t h e volt age s w i n g of c s co m p ca nn o t g o be l o w gr o u n d . t h i s seco n d a r y cu rr e n t limi t con t r o ls t h e in ter n al c o m p v o l t a g e t o t h e pwm co m p a r a t o r s t o 2 v . this limi ts t h e v o l t a g e dr o p acr o s s th e lo w- side mos f et s t h r o ug h t h e c u r r en t b a lan c e cir c ui t r y . ther e is als o a n in h e r e n t p e r phas e c u r r en t limi t t h a t p r o t e c ts i n d i v i d u a l ph a s e s i f one or more ph a s e s s t op s f u nc t i on i n g b e ca us e o f a f a u l ty co m p on en t. this limi t is b a s e d o n t h e max i m u m n o r m a l mo de c o mp vol t a g e.
adp3181 rev. 0 | page 13 of 24 dynamic vid the adp3181 incorporates the ability to dynamically change the vid input while the controller is running. this allows the output voltage to change while the supply is running and supplying current to the load. this is commonly referred to as vid on-the-fly (otf). a vid otf event can occur under either light load or heavy load conditions. the processor signals the controller by changing the vid inputs in multiple steps from the start code to the finish code. this change can be either positive or negative. when a vid input changes state, the adp3181 detects the change and ignores the dac inputs for a minimum of 400 ns. this time is to prevent a false code due to logic skew while the five vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar blanking functions for a minimum of 250 s to prevent a false pwrgd or crowbar event. each vid change resets the internal timer. power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range, if all of the vid dac inputs are high, or whenever the en pin is pulled low. pwrgd is blanked during a vidotf event for a period of 250 s to prevent false signals during the time the output is changing. the pwrgd circuitry also incorporates an initial turn-on delay time based on the delay ramp. the pwrgd pin is held low until the delay pin reaches 2.8 v. the time between when the pwrgd undervoltage threshold is reached and when the delay pin reaches 2.8 v provides the turn-on delay time. this time is incorporated into the soft-start ramp. to ensure a 1 ms delay time on pwrgd, the soft-start ramp must also be > 1 ms. refer to the application information section for detailed information on setting c dly . output crowbar as part of the protection for the load and output components of the supply, the pwm outputs are driven low (turning on the low-side mosfets) when the output voltage exceeds the upper crowbar threshold. this crowbar action stops once the output voltage falls below the release threshold of about 700 mv. turning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvoltage is due to a short of the high-side mosfet, this action current-limits the input supply or blows its fuse, protecting the microprocessor from destruction. output enable and uvlo the input supply (vcc) to the controller must be higher than the uvlo threshold and the en pin must be higher than its logic threshold for the adp3181 to begin switching. if uvlo is less than the threshold or the en pin is a logic low, the device is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and holds the ilimit pin at ground. in the application circuit, the ilimit pin should be connected to the od pins of the adp3418 drivers. because ilimit is grounded, this disables the drivers such that both drvh and drvl are grounded. this feature is important to prevent dis- charging of the output capacitors when the controller is shut off. if the driver outputs were not disabled, a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors.
adp3181 rev. 0 | page 14 of 24 04796- 0- 008 v in 12v v in rtn enable power good r lim 200k ? r ph1 124k ? fro m cpu r r 383k ? q2 ipd06n03l q5 ipd06n03l q8 ipd06n03l q1 ipd12n03l q3 ipd06n03l q4 ipd12n03l c dly 12nf v cc(core) 0.8375v ? 1.6v 65a avg, 74a p k v cc(core) rtn l2 600nh/1.6m ? l1 1.6 h c1 c6 r t 249k ? c12 100nf c21 c28 l3 600nh/1.6m ? c11 4.7 f d2 1n4148ws d3 1n4148ws d4 1n4148ws c8 100nf c7 4.7 f c9 4.7 f c13 4.7 f c17 4.7 f u2 adp3418 u3 adp3418 u4 adp3418 3 1 4 5 26 25 24 2 28 27 6 10 14 7 8 9 19 22 21 20 23 11 12 13 15 18 17 16 u1 adp3181 q7 ipd12n03l c16 100nf l4 600nh/1.6m ? c15 4.7 f r4 10 ? r a 16.9k ? c fb 33pf c a 390pf c cs1 2.2nf c cs2 1.5nf 470 f/16v 6 nichicon pw series 820 f/2.5v 8 fujitsu re series 8m ? esr (each) 10 f 23 mlcc in socket c18 4.7nf c14 4.7nf c10 4.7nf r3 2.2 ? rth 100k ? , 5% r2 2.2 ? r1 2.2 ? d1 1n4148ws r b 1.33k ? r cs1 35.7k ? c b 1.5nf r ph3 124k ? r dly 330k ? q9 ipd06n03l q6 ipd06n03l r sw1 * r sw3 * r sw2 * r cs2 73.2k ? r ph2 124k ? 1 2 3 8 7 6 4 5 bst in od vcc drvh sw pgnd drvl 1 2 3 8 7 6 4 5 bst in od vcc drvh sw pgnd drvl 1 2 3 8 7 6 4 5 bst in od vcc drvh sw pgnd drvl vid4 vid3 vid2 vid1 vid0 cpuid fbrtn fb comp en pwrgd delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 cscomp gnd cssum csref ilimit + + c19 1 f c20 33 f + + + *for a description of optional r sw resistors, see the theory of operation section. f i g u re 10. t y pic a l v r 10 a p p l i c at io n ci r c u i t
adp3181 rev. 0 | page 15 of 24 application information the desig n p a ram e t e rs f o r a typ i cal ad p3181 cpu a p p l ic a t io n are a s fol l ow s : ? inp u t v o l t a g e ( v in ) = 12 v ? vid s e t t in g v o l t a g e (v vi d ) = 1.500 v ? du ty c y c l e (d) = 0.125 ? n o minal o u t p u t v o l t a g e a t n o lo ad (v onl ) = 1.48 0 v ? n o minal o u t p u t v o l t a g e a t 65 a lo ad (v of l ) = 1. 3825 v ? st a t i c output vo lt age d r op b a s e d on a 1 . 5 m ? l o a d l i n e ( r o ) f r o m n o lo ad t o f u l l lo ad: v? = v onl C v ofl = 1.480 v C 1.3825 v = 97.5 mv ? ma x i mu m o u tp u t c u r r e n t ( i o ) = 65 a ? n u m b er o f phas es (n) = 3 ? sw it c h i n g f r e q u e n c y p e r p h a s e ( f sw ) = 330 kh z setti ng th e clock fr equency the ad p3181 u s es a f i xed-f r eq uen c y co n t r o l ar c h i t ec t u r e . th e f r eq uen c y is s e t b y a n ext e r n al timin g r e sis t o r (r t ). t h e c l o c k f r e q uen c y a nd t h e n u m b er o f phas es deter m ine t h e s w i t chin g f r e q u e nc y p e r p h a s e, w h i c h re l a te s d i re c t ly to s w itch i n g l o ss e s a nd t h e si zes o f t h e i n d u c t o r s and in p u t and o u t p u t ca p a c i to rs. w i t h n = 3 f o r thr e e p h as es, a c l o c k f r eq uen c y of 990 kh z s e ts th e swi t c h i n g f r eq ue n c y , f sw , o f e a ch phas e t o 3 30 khz, w h ich r e p r es en ts a p r ac t i cal t r ade - o f f b e tw e e n t h e s w i t chin g los s es and t h e si zes o f t h e o u t p ut f i l t er com p on e n ts. f i gu r e 6 s h o w s t h a t t o ac hieve a 990 kh z os cil l a t o r f r e q uen c y , the co r r ec t val u e f o r r t is 200 k?. f o r g o o d ini t ial acc u rac y a n d f r eq uen c y s t ab ili t y , i t is re c o m m e nd e d t o u s e a 1 % re s i stor . soft-start and current-limit latch-off delay time s b e ca us e t h e s o f t -s t a r t , pwr g d de l a y , an d c u r r en t-li mi t l a t c h- o f f de la y f u n c t i o n s al l s h a r e t h e d e l a y p i n, t h es e t h r e e p a ra m e ters m u st b e con s ider e d t o g e t h er . th e f i rs t s t ep is t o s e t c dl y f o r th e pwr g d d e la y ra m p . t h is ra m p is g e n e r a t e d wi t h a 20 a in t e r n al c u r r en t s o ur ce . th e va l u e o f r dl y has a s e cond- ord e r i m p a c t on t h e s o f t - s t a r t t i me b e c a u s e it s i n k s p a r t of t h e c u r r en t s o ur ce t o g r o u n d . h o w e v e r , as lo n g as r dl y is k e p t g r e a t e r t h a n 20 0 k?, t h is ef fe c t is mi n o r . the v a l u e fo r c dl y ca n b e a p p r o x im a t e d usin g ) ( ) ( v 8 . 2 2 v 8 . 2 a 20 uv pwrgd vid pwrgd dly uv pwrgd vid dly v v t r v v c ? ? ? ? ? ? ? ? ? ? ? ? ? = (1) w h er e t pwr g d is t h e desir e d p w rgd dela y t i me and v pwr g d(uv ) is th e un d e r v o l ta ge th r e s h o l d f o r t h e pw r g d co m p a r a t o r . a ssu ming an r dl y o f 250 k? a nd a desir e d a p w r g d dela y ti m e o f 1 s, c dl y i s 12 n f . t h e s o ft - s ta r t de la y tim e ca n th en be calc u l a t ed usin g dly vid vid dly ss r v v c t ? = 2 a 20 ( 2 ) on ce c dl y has b e en ch os en, r dl y ca n be calc u l a t ed f o r th e c u r r en t limi t l a tch o f f t i m e using: dly delay dly c t r = 2 ( 3 ) if t h e r e s u l t f o r r dl y is les s tha n 200 k?, a smal ler s o f t -s ta r t ti m e s h o u ld be co n s i d e r ed b y r e calcula t i n g t h e eq ua ti o n f o r c dl y , o r a lo n g er la t c h-o f f tim e sh o u ld be us e d . i n n o cas e sh o u ld r dl y be les s than 200 k?. i n this exa m p l e , a de l a y tim e o f 2 m s gi v e s r dl y = 333 k?. the c l os es t s t anda r d 5 % va l u e is 330 k?. s u bs ti t u t i n g 33 0 k? bac k in t o e q ua tion s 1 and 2 s h o w s tha t t h e pwrg d dela y a nd s o f t -st a r t t i m e s do n o t ch an ge sig n if ican t l y . induc t or s e lection the ch o i ce o f i n d u c t an ce fo r t h e ind u c t o r de t e r m i n es t h e r i p p l e c u r r en t in t h e i n d u c t o r . l e s s i n d u c t an ce le ads to m o r e r i p p le c u r r en t, w h ich i n cr e a s e s t h e ou t p u t r i p p le v o l t ag e a nd cond uc- tio n los s es in t h e m o s f et s, b u t al lo ws usin g s m al ler size ind u c t o r s an d , fo r a sp e c if ie d p e a k -t o - p e a k t r an sien t d e v i a t io n , les s t o tal o u t p u t ca p a ci tan c e . c o n v ers e l y , a hig h er ind u c t an ce m e an s lo w e r r i p p le c u r r en t a nd r e d u ce d cond uc t i o n los s es, b u t re qu i r e s l a r g e r - s i z e i n d u c t or s a n d more output c a p a c i t a nc e f o r t h e s a me p e a k -to-p e ak t r an sien t de v i a t io n. i n an y m u l t i p has e co n v er t e r , a p r ac t i cal val u e fo r t h e p e ak-t o-p e a k i n d u c t o r r i p p l e c u r r en t is les s t h a n 80 % o f t h e maxim u m dc c u r r en t in t h e s a m e i n d u ct o r . eq ua tio n 4 s h o w s th e r e la ti o n s h i p be tw ee n t h e i n d u cta n ce , osc i ll a t o r f r eq u e n c y , a n d peak -t o- peak ri p p l e c u r r en t in t h e i n d u c t o r . e q ua t i o n 4 det e r m i n es t h e mini m u m ind u c t an ce b a s e d o n a g i v e n o u tp u t r i p p le v o l t age: l f d v i sw vid ripple ? = ) 1 ( ( 4 ) ripple sw o vid v f d n d r v l ? ? )) ( 1 ( ) 1 ( (5) i n te l r e co mm e nds t h a t t h e r i p p l e v o l t a g e s h o u l d n o t exce e d 10 mv p e a k -t o-p e ak a t t h e s o ck et. s o l v in g e q u a tio n 4 f o r a 1 2 m v p e a k - t o - p e a k output r i ppl e vo lt age a t t h e re g u l a tor s output to a l l o w f o r d rop s t h roug h t h e p c b t r a c e s y i el d s ( ) nh 310 mv 12 khz 330 375 . 0 1 875 . 0 m 5 . 1 v 5 . 1 = ? ? l (6)
adp3181 rev. 0 | page 16 of 24 i f th e r i p p le v o l t a g e is les s than t h a t desig n e d f o r , th e ind u c t o r ca n be made smal ler un til th e r i p p le val u e is m e t. this al lo ws o p t i ma l t r a n sie n t r e sp on s e and mini m u m o u t p u t de co u p li n g . the s m a l l e st p o ss ibl e i n d u c t or s h o u ld be us e d to minimize t h e n u m b er o f o u t p u t c a p a ci t o rs. a 300 nh ind u c t or is a g o o d c h o i ce t o s t a r t, and i t g i v e s a c a lc u l a t e d r i p p le c u r r en t o f 13.3 a, whic h is 61 % o f th e f u l l lo ad c u r r en t o f 21.7 a. the ind u c t o r shou l d no t s a tu r a te a t t h e p e a k c u r r e n t of 2 9 a , an d s h ou l d b e a b le t o han d le t h e s u m o f the p o w e r dis s i p a t ion c a us ed b y t h e a v era g e c u r r en t o f 22 a in t h e w i ndin g an d t h e co r e los s . an o t h e r im p o r t a n t fac t o r in t h e ind u c t o r desig n is t h e d c r , w h ich is us e d for m e asur in g t h e phas e c u r r en ts. a la rge d c r ca us es exces s i v e p o w e r los s es, w h i l e t o o smal l a val u e le ads t o in cr e a s e d m e asur em en t er r o r . a g o o d r u le is to ha v e t h e d c r be abo u t 1 t o 1? tim e s t h e dr o o p r e sis t a n ce (r o ). designing an inductor on ce t h e i n d u c t a n c e an d d c r a r e kn own, t h e n e xt st ep is t o d e s i g n a n i n d u c t or or f i nd a st a n d a rd i n d u c t or t h a t c o me s a s clos e as p o s s i b le t o m e et in g t h e o v eral l desig n g o als. i t is als o im p o r t an t t o h a ve t h e i n d u c t ance an d d c r t o l e ra n c e sp e c if ie d t o k e ep t h e acc u rac y o f th e sys t em co n t r o l l ed . u s in g 15% f o r th e ind u c t an ce an d 8% fo r t h e d c r (a t r o o m tem p e r a t ur e) a r e r e as o n a b le t o ler a n c es tha t m o s t ma n u fac t ur ers c a n m eet. the f i rs t decision in desig n ing th e ind u c t o r is to c h o o s e t h e c ore m a te r i a l . s e ve r a l p o ss i b i l it i e s f o r prov i d i n g l o w c ore l o ss a t hig h f r e q ue ncies in cl ude t h e p o w d er co r e s (k o o l-m? f r o m m a g n etics, i n c. o r m i cr o m etals ) a n d the ga p p e d s o f t f e r r i t e c ore s ( 3 f 3 or 3f 4 f rom ph i l ip s ) . l o w f r e q u e nc y p o wd e r e d i ron c ore s s h ou l d b e a v oi d e d d u e to t h e i r h i g h c ore l o ss , es p e c i al ly w h en t h e i n d u c t o r va l u e is r e la t i v e l y l o w a n d t h e ri p p l e cu rr e n t i s h i gh . the bes t ch o i ce f o r a co r e g e o m etr y is a c l os ed-lo o p typ e s, s u c h a s p o te n t i o me te r c ore s , p q , u , an d e c ore s , or toroi d s . a go o d co m p r o m is e b e t w e e n p r ice and p e r f o r ma n c e a r e co r e s w i t h a t o r o idal sha p e . ther e a r e man y us ef u l r e fer e n c es fo r q u ickly desig n in g a p o w e r ind u c t o r , such as ? m a g n et ic d e s i g n er s o f t wa r e i n t u s o f t (h t t p://w w w . in t u so f t .co m ) ? d e sig n in g m a g n et ic c o m p on e n ts fo r h i g h f r e q uen c y d c -d c c o n v er t e rs, m c l y ma n, kg m a g n et ics, is b n 1 - 883107-00-08 selecting a st an da rd in du ct or the co m p anies lis t ed in t a b l e 6 ca n p r o v ide des i g n co n s u l ta t i on a n d de li v e r po wer in d u ct o r s o p t i m i ze d f o r high po w e r ap p l i c at i o n s u p o n r e q u e s t . table 6. pow e r i n ductor manuf a cturers c o m p a n y c o n t a c t w e b s i t e coilcraft (847) 639-640 0 http://www.coilcraft.com coiltronics (561) 752-500 0 http://www.c o iltronics.c o m sumida electric company (510) 668-066 0 http://w ww.su mid a.com v i s h a y ( 4 0 2 ) 563-650 6 http://www.vi s h a y . c o m outpu t droop resis t ance the desig n r e q u ir es t h a t t h e r e g u la t o r o u t p u t v o l t a g e m e as ur e d a t t h e cp u p i n s dr o p s when t h e o u t p u t c u r r en t in cr eas e s. th e sp e c i f i e d vo lt ag e d rop c o r r e s p o nd s to a d c output re s i st a n c e (r o ). the o u t p u t c u r r en t is m e as ur e d b y s u mmin g t o get h er t h e vo lt age a c ro ss e a ch i n d u c t or a n d t h e n p a ss i n g t h e s i g n a l t h r o u g h a lo w-p a ss f i l t er . this summ e r -f i l t e r is t h e cs a m plif ie r c o n f i g u r e d w i t h re s i stor s r ph (x) (sum m e rs) and r cs and c cs (f il t e r). th e o u t p u t r e sis t an ce of th e r e gu l a t o r is s e t b y th es e e q u a t i o n s, w h ere r l i s t h e d c r of t h e output i n d u c t or s : l x ph cs o r r r r = ) ( ( 7 ) cs l cs r r l c = ( 8 ) on e has t h e f l exi b i l i t y o f ch o o sin g ei t h er r cs or r ph (x). it i s b e s t to st ar t w i t h r ph (x) in t h e ra n g e o f 100 k? t o 200 k?, a n d t h en so l v e f o r r cs b y r e a r ra n g in g e q ua tion 7. u s in g 100 k? f o r r ph ( x ) : k 8 . 93 k 100 m 6 . 1 m 5 . 1 ) ( = = = n e xt , use eq ua tio n 8 t o so l v e f o r c cs : nf 0 . 2 k 8 . 93 m 6 . 1 nh 300 = = the clos es t s t a n da r d val u e fo r c cs is 1.8 nf . i f the calc u l a t e d val u e is n o t a st a n da rd val u e , r e calc u l a t e fo r t h e clos es t 1% re s i stor v a lu e s f o r r cs an d r ph (x) usin g th e f i nal val u e s e lec t ed fo r c cs . this can b e q u ick l y ca l c u l a t e d b y m u l t i p lyin g t h e o r ig ina l va l u es o f r cs an d r ph (x) b y th e ra ti o o f th e calcula t ed c cs t o t h e ac t u a l val u e us e d . f o r b e s t acc u rac y , c cs shou l d b e a 5% o r 10% np o ca p a c i t o r . f o r this exa m p l e , th e ac t u a l val u es us ed f o r r cs an d r ph (x) a r e 104.2 k? a n d 111.1 k?. the c l os es t st andard 1 % v a lu e for r ph (x ) is 110 k?. r cs is used l a t e r and shou l d no t b e rou nd e d y e t .
adp3181 rev. 0 | page 17 of 24 inductor dcr temperature correction w i t h t h e i n d u c t o r s d c r b e i n g us e d as t h e s e n s e e l e m en t, a n d co p p er wir e b e i n g t h e s o ur c e o f t h e d c r , on e n e e d s t o co m p e n s a t e fo r t e m p era t ur e cha n g e s o f t h e i n d u c t o r s wi nding. f o r t una t e l y , co pp er has a we l l k n o w n t e m p er a t ur e co ef f i cien t (t c) o f 0.39%/c. if r cs is desig n e d t o ha ve a n op p o si t e and eq ua l p e r c en t a g e cha n g e i n r e sis t a n c e t o t h a t o f t h e wir e , i t cancels t h e t e m p er - a t ur e v a r i a t io n o f t h e i n d u c t o r s d c r . d u e t o t h e n o nli n e a r n a tu re of n t c t h e r m i stor s , r e s i stor s r cs 1 an d r cs 2 a r e n eed e d (s e e f i gur e 11) to lin e a r i z e t h e nt c a n d p r o d u c e t h e desir e d t e m p era t ur e t r ackin g . 04796-0-009 cssum 18 cscomp place as close as possible to nearest inductor or low-side mosfet 17 csref 16 adp3181 c cs 1.8nf r cs1 r th r cs2 keep this path as short as possible and well away from switch node lines to switch nodes to v out sense r ph1 r ph3 r ph2 f i gure 11. t e mpe r a t ur e com p ensat i o n circuit v a l u es the fol l o win g pr o c e d ur e yie l ds val u es t o us e fo r r cs 1 , r cs 2 , a n d r th (th e t h er mis t o r val u e a t 25c) f o r a g i v e n r cs val u e . 1. s e lec t an nt c to be us ed bas e d o n typ e an d val u e . b e ca us e t h er e is n o t a va l u e yet, s t a r t w i t h a t h er mis t o r wi t h a v a l u e cl o s e to r cs . the ntc sh o u ld a l s o ha v e a n ini t ial t o lera n c e of b e tte r t h an 5 % . 2. b a s e d on t h e t y p e of n t c , f i n d it s rel a t i v e re s i st an c e v a lu e a t t w o t e m p era t ur es. th e t e m p e r a t ur es t h a t w o rk w e l l a r e 50c an d 90 c. w e cal l t h es e r e sis t a n c e val u es a (a is r th (50c)/r th (25c)) a n d b (b is r th (90c)/r th (25c)). the nt c s r e la t i v e val u e is al wa ys 1 a t 25c. 3. f i n d th e r e la ti v e v a l u e o f r cs r e q u i r ed f o r ea c h o f th e s e t e m p era t ur es. this is b a s e d o n t h e p e r c en t a g e cha n g e n e e d e d , w h ich c a n b e 0.39 %/ c ini t ial l y . th es e v a l u es a r e r 1 (r 1 is 1/(1+ t c (t 1 ? 25))) a n d r 2 (r 2 is 1/(1 + t c (t 2 ? 25))) wher e t c = 0.0 039, t1 = 50c, a n d t2 = 90c. 4. c o m p u te t h e r e la t i ve val u es fo r r cs 1 , r cs 2 , a n d r th : () () () () () ( ) ? ? ? ? ? ? + ? ? ? = 1 1 1 1 (9) () ? ? ? ? = 1 1 1 cs1 cs2 th r r r 1 1 1 1 ? ? = ca l c ul a t e r th = r th r cs , t h en s e le c t t h e clos es t val u e o f t h er mis t o r a v a i l a b l e . a l s o co m p u t e a s c aling fac t o r k b a s e d on th e ra ti o o f th e a c t u al t h e r m i s t o r v a l u e used r e la ti v e t o t h e co m p u t ed one: ( ) () = ( 1 0 ) c a lc u l a t e va l u es fo r r cs 1 an d r cs 2 usin g t h e fol l o w in g: cs1 cs cs1 r k r r = ( 1 1 ) )) ( ) 1 (( cs2 cs cs2 r k k r r + ? = fo r t h i s e x a m p l e , r cs h a s a l r e a d y b e e n c a l c ul a t ed i n th e p r evio us s e c t ion t o b e 104.2 k?, s o a th er mis t o r val u e o f 100 k? is s t a r t e d wi th. i n a v a i lab l e 0603 size ther mis t o r s, th er e is a v i s h a y nths0603n01 n1003jr nt c t h er mis t o r wi t h a = 0.3602 a n d b = 0.0917 4. f r o m th es e , r cs 1 = 0.3796, r cs 2 = 0.7195 a n d r th = 1.0751 ca n be com p u t ed. s o l v in g f o r r th yie l ds 112.05 k?, s o wh en 100 k? is c h os en, k = 0.8925. f i nal l y , r cs 1 and r cs 2 a r e f o un d t o be 35 .30 k? an d 78.1 1 k?. s e lec t ing t h e cl o s e s t 1 % re s i stor v a lu e s y i el d s a c h oi c e of 3 5 . 7 k ? or 78.7 k?. outpu t o f fset the i n t e l sp e c if ica t ion r e q u ir es t h a t , a t n o lo ad , t h e n o mina l o u t p ut v o l t a g e of t h e r e gu l a t o r b e o f fs et t o a lo w e r val u e t h a n t h e n o minal v o lt a g e co r r es p o n d in g t o t h e vid c o de . th e o f fs et is s et b y a co n s t a n t c u r r en t s o urce f l o win g o u t of t h e fb p i n (i fb ) an d f l ow i n g t h rou g h r b . th e va l u e o f r b ca n be f o u n d usin g e q ua tion 12. th e c l os es t sta n da r d 1% r e sis t o r val u e is 1.3 3 k?. fb onl vid b i v v r ? = ( 1 2 ) k 33 . 1 a 15 v 480 . 1 v 5 . 1 = ? = c ou t selection t h e re qu i r e d output d e c o upl i ng f o r t h e re g u l a to r i s t y pi c a l l y r e c o m m e n d ed b y i n t e l f o r v a rio u s p r oc e s so r s a n d p l a t f o rm s . on e can als o us e s o me sim p le desig n guide l i n es t o det e r m i n e w h a t is r e q u ir e d . th es e guide l i n es a r e b a s e d o n ha vin g b o t h b u l k and cera mic ca p a c i t o rs in th e sys t em.
adp3181 rev. 0 | page 18 of 24 t h e f i r s t th i n g i s t o se l e ct th e t o tal a m o u n t o f ce ra m i c ca pa c i - ta nce . this is bas e d on the n u m b er an d typ e o f ca p a c i t o r t o b e used . th e be s t loca ti o n f o r ce ra m i cs is in sid e t h e s o ck et, wi t h 12 t o 18 o f size 1206 bein g the p h ysical limi t. oth e rs can be place d alo n g t h e o u t e r e d g e o f t h e s o ck et as we l l . the com b in e d c e ra mic val u es of 200 f t o 300 f a r e r e co m- m e n d ed , made o f m u l t i p le 10 f o r 22 f ca p a ci t o rs. s e lec t t h e n u m b er o f cera mics an d f i nd t h e t o tal cera mic ca p a ci tan c e (c z ). n e xt, t h er e is a n u p p e r limi t i m p o s e d on t h e t o t a l am o u n t o f b ulk ca pa c i ta n c e (c x ) w h en one co n s iders t h e vid o n -t he-f ly v o l t a g e st ep p i n g o f t h e o u t p u t (vol t a g e st ep v v in tim e t v ), an d a lo w e r li m i t ba se d o n m eeti n g t h e cri t i c al ca pa ci t a n c e f o r loa d r e le as e fo r a g i ven maxi m u m lo ad step i max : ? ? ? ? ? ? ? ? ? z vid o step min x c v r n i l c ) ( ( 1 3 ) ( ) max x c z o v vid v vid v o c l nkr v v t v v r nk l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 2 2 ? ? ? ? ? ? ? ? = v err v v n k 1 where ( 1 4 ) w h er e r x is t h e es r o f t h e b u l k ca p a c i t o r b a n k . t o m e et t h e t r a n sien t sp e c if i c a t ion, r x canno t be g r e a t e r tha n 3 tim e s r o . if t h e c x(min) is l a rg er tha n c x(ma x) , t h e sys t e m do es n o t me et t h e vid o n -t he-f ly sp e c if ic a t ion and ma y r e q u ir e t h e us e o f a smal ler in d u c t or o r m o r e p has es (a nd ma y ha v e t o in cr eas e t h e sw i t chin g f r e q u e n c y t o k e ep t h e o u t p ut r i p p le t h e s a me). i n this exam p l e , th er e a r e tw e l ve 22 f 1206 ml c c a p a ci t o rs (cz = 264 f). the vid-o n -the-f l y s t ep c h a n ge is 12.5 mv in 5 s . s o l v i n g f o r th e b u lk ca pa ci ta n c e , a s s u m i n g th a t r x = r o , a nd w h er e k = 4.6, yie l ds () mf 92 . 5 f 230 v 5 . 1 m 3 . 1 3 a 60 nh 600 = ? ? ? ? ? ? ? ? ? ? min x c () ? v 5 . 1 m 3 . 1 6 . 4 3 mv 250 nh 600 2 2 max x c mf 9 . 23 f 230 1 nh 320 mv 450 m 3 1. 4.6 3 v 5 1. s 150 1 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + u s in g t e n 560 f osco n s wi t h a n e s r o f 12 m? eac h yie l ds c x = 5.6 mf wi t h a n r x = 1.2 m? (makin g t h e new limi ts o n c x 2.4 mf t o 8.8 mf , whic h is s t il l wi t h in t h e accep t a b le ra n g e). on e last che c k sh o u ld b e made t o en s u r e t h a t t h e esl o f t h e bu l k c a p a c i t o r s ( l x ) is lo w en o u g h t o limi t t h e ini t ial hig h f r e q uen c y t r a n sien t sp i k e . this ca n be t e s t e d usin g ph 89 3 m 3 . 1 f 230 2 = ? x 2 o z x l r c l (15) in t h i s e x a m p l e , l x is 400 ph f o r th e t e n os cson c a p a ci t o rs, wh i c h s a ti s f i e s t h i s li m i ta ti o n . i f th e l x o f t h e chos en b u l k c a p a c i tor b a n k i s to o l a rge, t h e n u m b e r of m l c c a p a c i tors m u st be in cr eased . n o t e tha t f o r this m u l t im o d e con t r o l t e c h niq u e , al l cera mic desig n s can be us e d as lo n g as th e co n d i t i o n s o f eq ua ti o n s 11, 12, a n d 13 a r e s a tisf ied . power mosfets f o r th i s e x a m p l e , th e n - c h a n n e l po w e r m o s f e t s ha v e been se l e ct e d f o r o n e h i gh - s id e swi t c h a n d t w o l o w - s i d e sw i t c h e s pe r p h ase . th e ma in se lectio n pa ram e t e r s f o r th e p o w e r m o s f et s are v gs(th ) , q g , c is s , c rs s , a nd r ds( o n ) . th e mini m u m g a te dr i v e v o l t a g e (t h e s u p p l y v o l t a g e t o the ad p3418) dic t a t es w h et h e r s t anda r d thr e shold o r log i c-lev e l thr e s h old m o s f et s m u s t be use d . w i th v ga te ~10 v , log i c - lev e l thr e sh old m o s f et s (v gs(th ) < 2.5 v) a r e r e co mm ended . the maxi m u m o u t p ut c u r r en t, i o, deter m in e s t h e r ds(o n ) r e q u ir em e n t fo r t h e lo w-side (s yn chr o n o us) mos f et s. i n t h e ad p3181, c u r r e n ts a r e ba lan c e d betw een p h as es , s o th e c u r r en t in e a ch lo w-side mos f et is t h e o u t p u t c u r r en t divide d b y t h e tot a l n u mb e r of mo sf e t s ( n sf ) . w i th co n d uctio n los s e s bei n g do minan t , t h e fol l o w in g exp r es sio n sh o w s t h e to t a l p o w e r b e i n g dis s i p a t e d in e a c h sy n c hr on o u s m o s f et in t e r m s o f th e r i p p le c u r r en t p e r phas e (i r ) a n d a v er a g e t o t a l o u t p u t c u r r en t (i o ). () ( ) sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = 2 2 12 1 1 (16) kno w i ng t h e m a x i m u m o u tput c u r r e n t b e i n g d e s i g n e d f o r an d t h e max i m u m a l l o we d p o wer dissi p a t ion, o n e c a n f i n d t h e re qu i r e d r ds(o n ) f o r th e m o s f et . f o r d-p a k m o s f et s u p t o a n am b i e n t t e m p era t ur e o f 50c, a s a fe limi t fo r p sf is 1 w (as s u min g 2 d-p a ks) a t 120c j u n c tion t e m p er a t ur e . h e r e , f o r exa m ple (65 a maxim u m), r ds( s f) (per m o s f e t ) < 8.7 mw . this r ds(s f ) is also a t a j u n c tio n tem p er a t ur e o f abo u t 120 c, so t h is m u st b e acc o un t e d fo r t h is w h en ma k i n g t h is s e le c t ion.
adp3181 rev. 0 | page 19 of 24 a n ot he r i m p o r t an t f a c t or f o r t h e s y nc h r o n ou s mo sf e t i s t h e i n p u t c a p a ci t a nce and fe e d b a ck c a p a ci t a n c e . the ra t i o o f th e f eed ba c k t o i n p u t n eed s t o be s m all (le s s th a n 10% i s r e co m m e n d e d ) t o p r ev en t a c ci d e n t al t u rn - o n o f th e syn c hr o n o u s mos f et s w h e n t h e s w i t ch n o de g o es hig h . als o , t h e t i m e to swi t c h t h e sy nc hr o n o u s m o s f et s o f f s h o u ld n o t exce e d t h e n o n-o v erla p de ad t i m e o f t h e m o s f et dr i v er (40 n s typ i cal f o r th e adp3418). th e o u t p u t im p e dan c e o f t h e dr i v er is ab ou t 2 ?, a n d t h e t y p i cal m o s f et in p u t g a t e r e sis t a n ces a r e abo u t 1 ? C 2 ?, s o a t o tal ga t e c a p a ci t a n c e o f les s tha n 6000 pf s h o u ld be adher e d t o . b e c a us e t h er e a r e t w o m o s f e t s in pa rall e l , th e i n p u t ca pa c i ta n c e f o r ea c h syn c hr o n o u s mos f et sh o u ld be limi ted t o 3000 pf . t h e hig h -side (m a i n) m o s f et has t o b e a b le to ha n d le tw o m a in p o w e r dissi p a tio n co m p o n en ts: co nd uc tio n an d swi t ching los s es. th e s w i t chin g los s is r e l a t e d t o t h e am oun t o f t i m e i t t a k e s for t h e mai n mo s f e t to tu r n on and of f, and to t h e c u r r en t a n d v o l t a g e t h a t a r e b e i n g s w i t che d . b a sin g t h e s w i t ch- in g s p eed o n t h e r i se a n d fal l tim e o f t h e ga t e dr i v er im p e dan c e a n d m o s f et i n p u t ca p a c i t a n c e , t h e fol l o w in g exp r es sio n p r o v ides a n a p pr o x ima t e v a l u e fo r t h e s w i t chi n g los s p e r ma in m o s f et , w h er e n mf is th e t o tal n u m b er o f m a in m o s f et s: () iss mf g m f o cc sw mf s c n n r n i v f p = 2 (17) he r e , r g is th e to tal ga t e r e sis t an ce (2 ? f o r th e ad p3418 a nd ab o u t 1 ? fo r typ i cal hig h sp e e d s w i t chin g m o s f et s, ma k i n g r g = 3 ?), a n d c is s is t h e i n p u t c a p a ci t a n c e o f t h e ma in mos f e t . i t is in t e r e st in g to n o t e t h a t a ddi n g m o r e ma i n mo s f e t s ( n mf ) do es n o t r e al ly h e l p t h e s w i t chi n g los s p e r m o s f e t bec a use th e a d di ti o n al g a t e ca pa ci ta n c e s l o w s d o w n swi t c h in g. th e bes t t h in g t o r e d u ce s w i t c h in g los s is t o us e lo w e r ga t e ca p a ci tan c e de vices. the co n d uc tio n los s o f th e ma in m o s f et is g i v e n b y th e fol l o w in g, w h er e r ds(m f) is th e o n r e sis t an ce o f t h e m o s f et : () ( ) mf ds mf r mf o mf c r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 2 2 12 1 (18) t y p i cal l y , fo r ma in m o s f et s, on e w a n t s t h e hi g h est s p e e d (lo w c is s ) de vic e , b u t t h es e usu a l l y ha v e hig h er o n r e sis t an ce . on e m u s t s e le c t a de vic e t h a t me ets t h e t o t a l p o w e r dis s i p a t io n (a bo u t 1.5 w f o r a sin g le d-p a k) w h en com b inin g t h e sw i t ch in g and c o nd uc t i o n lo ss e s . f o r this exa m p l e , a n i n f i n e on i p d12n03l was s e lec t e d as t h e ma in m o s f et (thr ee t o tal; n mf = 3), wi th a c is s = 1460 pf (m ax) a n d r ds(m f) = 14 m? (max a t t j = 120o c), a nd an i n f i n e on i p d 0 6 n 0 3 l a s t h e s y n c h r onou s mo sf e t ( s i x tot a l ; n sf = 6), wi th c iss = 2370 pf (m ax) a n d r ds(s f) = 8.3 m? (m ax a t t j = 120oc). the sy n c hr o n o u s m o s f et c is s is les s tha n 3000 pf , s a tisf yi n g tha t r e q u ir em en t. s o lvin g fo r th e p o w e r dissi p a t io n p e r mos f et a t i o = 65 a an d i r = 13 a yie l ds 900 mw fo r e a c h sy n c hr on o u s m o s f et a nd 1.6 w fo r e a c h ma in m o s f et . th es e n u m b ers w o rk w e l l co n s ider ing t h a t t h er e is us ual l y m o r e p c b a r ea a v a i lab l e fo r eac h ma in m o s f et v e rs us e a ch sy n c hr on ous mos f e t . on e last t h in g to co n s ider is t h e p o w e r dis s i p a t io n i n t h e dr i v e r f o r eac h p h as e . this is bes t des c r i be d in t e r m s o f th e q g fo r t h e m o s f et s a nd i s g i v e n b y t h e fol l o w in g, w h er e q gmf i s th e t o tal ga t e c h a r g e f o r eac h ma in m o s f et a nd q gs f i s th e t o tal g a t e c h a r g e fo r e a c h syn c hr o n o u s mos f et : () cc cc gsf sf gmf mf sw drv v i q n q n n f p ? ? ? ? ? ? ? ? + + = 2 (19) a l s o sh o w n is t h e st and b y dissi p a t io n fac t o r ( i cc v cc ) f o r th e dr i v er . f o r th e ad p3418, th e maxim u m dis s i p a t io n sh o u l d b e les s tha n 400 mw . f o r exa m p l e , wi t h i cc = 7 ma, q gmf = 22.8 nc and q gs f = 34.3 nc, 260 mw is f o und in e a c h dr i v er , which is b e lo w t h e 400 mw dissi p a t ion limi t. ramp resistor selection the r a m p r e sisto r ( r r ) is us e d fo r s e t t ing t h e si ze o f t h e i n t e r n a l p w m r a m p . t h e v a lu e of t h i s re s i stor i s cho s e n to prov i d e t h e b e st com b ina t ion o f t h er ma l b a l a n c e, st ab i l i t y , and t r a n sie n t r e s p o n s e . the fol l o w in g exp r es sio n is us e d fo r det e r m ini n g t h e opt i m u m v a lu e : k 81 3 pf 5 m 2 . 4 5 3 nh 0 60 0.2 3 = = = r r ds d r r r c r a l a r (20) w h er e a r is t h e in t e r n a l ram p am plif ier ga in, a d is t h e c u r r en t bala n c in g a m p l if i e r ga i n , r ds is th e t o tal lo w-side m o s f et o n re s i st anc e , an d c r is the in t e r n al ra m p c a p a ci t o r val u e . the c l os es t s t anda r d 1% r e sis t o r val u e is 226 k?. the i n t e r n al ram p v o l t a g e ma g n i t ude can b e c a lc u l a t e d usin g ( ) () v m 51 . 0 khz 267 pf 5 k 83 3 v 5 1. 125 0. 1 0.2 1 = ? = ? = r sw r r vid r r v f c r v d a v (21) t h e size o f the in t e r n al ra m p can b e m a de la r g er o r sm al ler . i f i t is made la rger , st a b i l i t y and t r a n sien t r e sp on s e i m p r o v e, b u t t h er mal b a l a n c e deg r ades. l i k e wis e , if t h e ram p is made smal ler , t h er mal b a l a n c e im p r o v es a t t h e s a cr if ice o f t r a n sien t r e s p on s e an d st a b i l it y . t h e f a c t or of 3 i n t h e d e nom i n a tor of e q u a t i o n 2 0 s e ts a ram p si ze t h a t g i v e s an o p t i ma l b a l a n c e for go o d st ab i l i t y , t r a n sien t r e sp on s e , an d t h er ma l balan c e .
adp3181 rev. 0 | page 20 of 24 current limit setpoint t o s e le c t t h e c u r r en t limi t s e t p o i n t , i t is n e ces s a r y t o f i n d t h e re s i stor v a lu e f o r r lim . the c u r r en t limi t t h r e shold fo r t h e ad p3181 is s e t wi t h a 3 v s o ur ce (v lim ) acr o s s r lim wi th a ga in o f 10 mv/a ( a lim ). r lim can b e fo u n d usin g t h e fol l o w in g: o lim lim lim lim r i v a r = ( 2 2 ) wher e i lim is t h e a v era g e c u r r en t limi t fo r t h e o u t p u t o f t h e s u p p l y . f o r exa m p l e , usin g 90 a f o r i li m , r lim is 222.2 k? an d f o r whic h 221 k? c a n be ch os en as th e n e a r est 1% val u e . the p e r phas e c u r r en t limi t de s c r i b e d e a rlier has i t s li mi t deter m i n e d b y t h e fol l o w in g: () () 2 r max ds d bias r max comp phlim i r a v v v i + ? ? ? ( 2 3 ) wher e t h e maxi m u m c o mp v o l t a g e ( v co mp ( m a x ) ) is 3.3 v , t h e c o mp p i n b i as v o l t a g e ( v bi a s ) is 1.2 v , a n d t h e c u r r en t bala n c in g a m p l if i e r ga i n ( a d ) is 5. u s in g v r o f 0. 7 v , a nd r ds(m ax ) o f 5.3 m? (lo w -side on r e sis t an ce a t 1 50c), th er e is a p e r - ph as e li mi t o f 52 a. t h is limi t c a n b e ad j u s t ed b y c h a n g i n g t h e ram p v o l t a g e v r , b u t mak e s u r e n o t to s e t t h e p e r - phas e limi t lo w e r t h a n t h e a v era g e pe r - p h ase cu rr e n t (i lim / n ). feedback loop comp ensation de sign op timize d com p en s a tio n o f t h e ad p3181 al lo ws th e best p o ss ibl e re sp ons e of t h e re g u l a t o r s ou t p ut to a l o ad change. t h e basis fo r det e r m inin g t h e o p t i m u m co m p en s a t i o n is t o ma k e t h e re g u l a tor and ou tpu t d e c o upl i ng a p p e ar as an out p u t im p e dan c e t h a t is en t i r e ly r e sis t iv e o v er t h e wides t p o s s ib le f r e q uen c y r a n g e, in cl ud in g dc, and e q u a l to t h e dr o o p r e sist a n c e (r o ). w i t h t h e r e sis t i v e o u t p u t i m p e dance , t h e o u t p u t v o l t a g e dr o o ps in p r o p o r tio n t o th e lo ad c u r r en t a t an y lo ad c u r r en t s l ew ra t e ; th i s en s u r e s o p ti m a l pos i ti o n i n g a n d allo w s th e mini miz a t i on of t h e o u tp u t d e c o u p lin g . w i t h t h e m u l t im o d e f e e d back s t r u c t ur e o f th e ad p3181, o n e n e e d s t o se t t h e f eed ba ck co m p en sa ti o n t o m a k e th e co n v e r t e r s o u t p ut im p e dance w o rk in g in p a ra l l e l w i t h t h e o u t p ut de co u p lin g me e t t h is go a l . s e ve r a l p o les a nd ze r o s cr e a te d b y th e o u t p u t in d u ct o r a n d d e c o u p l i n g ca pa c i t o r s (o u t p u t f i l t e r ) ne e d to b e c o m p e n s a te d for . a t y pe- t h r ee co m p en sa t o r o n t h e v o l t a g e f e e d b a c k i s a d e q ua t e f o r prop e r c o m p e n s a t i on of t h e output f i lte r . t h e f o l l ow i n g e q u a t i o n s a r e in tende d to y i el d a n o p t i ma l st a r t i n g p o i n t fo r t h e desig n ; s o m e min o r ad j u s t men t s ma y b e n e ces s a r y t o acco un t f o r pcb a n d co m p o n en t pa rasi tic ef f e cts. u s in g e q u a t i on s 24 t o 28, t h e f i rs t s t ep is t o co m p u t e t h e t i me co n s t a n t s fo r al l o f t h e p o les and zer o s in t h e sys t em, w h er e , fo r th e ad p3181, r is th e pcb r e sis t a n ce f r o m t h e b u l k c a p a ci t o rs t o t h e ceramics a nd w h er e r ds is a p p r o x ima t e l y t h e t o t a l lo w- side m o s f et o n r e sis t an ce p e r p h as e a t 25c. f o r this exa m p l e , a d is 5, v r eq uals 1 v , r is a p p r o x ima t e l y 0.6 m? (assumin g a 4-la yer m o t h er b o a r d) a nd l x is 400 ph f o r th e 10 oscso n c a pa ci t o r s . ( ) vid o x rt vid rt l ds d o e v r c n v d n l v v r r a r n r ? + + + = 1 2 ( 2 4 ) ( ) m 9 . 37 v 5 1. m 3 1. mf 56 . 6 3 v 63 0. 375 0. 1 nh 600 2 v 5 1. v 63 0. m 6 1. m 2 . 4 5 m 3 1. 3 = ? + + + = e r () () s 79 . 4 m 0 1. m 0.6 m 3 1. m 3 1. ph 75 3 m 6 0. m 3 1. mf 56 . 6 ' ' = ? + ? = ? + ? = x o o x o x a r r r r l r r c t (25) ( ) ( ) ns 97 . 1 mf 56 . 6 m 3 1. m 6 0. m 0 . 1 ' = ? + = ? + = x o x b c r r r t ( 2 6 ) s 2 . 6 m 9 . 37 v 5 1. khz 267 2 m 2 . 4 5 nh 600 v 63 0. 2 = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? = e vid sw ds d rt c r v f r a l v t ( 2 7 ) () () ns 521 m 3 1. f 230 m 6 0. m 3 1. mf 56 . 6 m 3 . 1 f 230 mf 56 . 6 ' 2 2 = + ? ? = + ? = o z o x o z x d r c r r c r c c t ( 2 8 )
adp3181 rev. 0 | page 21 of 24 the co m p en s a t i o n val u es can b e s o lv e d usin g t h e fol l o w in g: pf 371 k 33 1. m 79 . 3 s 79 . 4 m 3 1. 3 = = = a b e a o a c r r t r n c ( 2 9 ) k .7 6 1 pf 71 3 s 2 . 6 = = = a c a c t r (30) nf 48 . 1 k 33 1. s 97 . 1 = = = b b b r t c (31) pf 2 . 31 k .7 6 1 ns 521 = = = a d fb r t c (32) c h o o sin g t h e cl os est st anda r d v a l u es fo r t h es e c o m p on e n ts yie l d s c a = 820 pf , r a = 7.87 k? , c b = 1.2 nf , a n d cfb = 100 pf . t h ese m a k e a g ood s t a r ti n g po in t . u s in g t h e desig n s p r e adsheet yie l ds m o r e op t i mal co m p en- sa ti o n v a l u e s ; f r o m th e s p r e a d s h eet , c a = 680 pf , r a = 5.49 k?, c b = 1.2 nf , a n d c fb = 68 pf . c in selection a n d in p u t current di/dt reduction i n con t in uo us ind u c t o r -c ur r e n t m o de , t h e s o u r ce c u r r en t o f th e h i gh - s id e m o s f et i s a p p r o x im a t e l y a sq ua r e w a v e wi th a d u ty ra tio eq ual t o n v ou t /v in a n d an a m pl itu d e of one - n t h of t h e maxim u m o u t p u t c u r r en t. t o pr e v en t la rg e v o l t a g e t r a n sie n ts, a lo w es r in p u t ca paci t o r size d fo r th e m a xim u m r m s cur r en t mu s t b e u s e d . t h e m a x i mu m r m s c a p a c i t o r c u r r e n t i s g i v e n b y a 5 . 10 1 125 0. 3 1 a 65 125 . 0 1 = ? = = crms o crms i d n i d i (33) n o t e tha t t h e ca p a ci t o r ma n u f a c t ur er s r i p p le c u r r en t ra tin g s ar e o f t e n b a s e d o n o n l y 2000 h o urs o f lif e . this mak e s i t advis a b l e t o f u r t h e r dera te th e ca p a c i t o r , o r t o c h o o s e a c a p a ci t o r r a t e d a t a hig h er t e m p er a t ur e than r e q u ir ed . s e veral ca p a ci t o rs ma y be p l ace d in p a ral l e l t o m e et size or h e ig h t r e q u ir em en ts in t h e desig n . i n this exa m p l e , th e in p u t c a p a ci t o r ban k is f o r m ed b y thr e e 2200 f , 1 6 v n i c h ico n ca p a ci t o rs wi th a r i p p le c u r r en t ra tin g o f 3.5 a e a c h . t o r e d u ce t h e in p u t-c u r r en t di/ d t t o b e lo w t h e r e co mme n d e d m a x i m u m of 0 . 1 a / s , note t h at an a d d i t i on a l s m a l l i n d u c t or (l > 1 h @ 15 a) s h o u l d b e i n se r t ed be tw een th e co n v e r t e r a n d t h e s u p p l y b u s. this ind u c t o r als o ac ts as a f i l t er betw een t h e con v er t e r and t h e p r ima r y p o w e r s o ur ce .
adp3181 rev. 0 | page 22 of 24 building a switchabl e vr9/vr10 design s o m e d e s i gn s ma y r e q u i r e th e a b ili t y t o w o r k wi th ei th e r a v r 9- o r a vr10-b a s e d cpu , b e ca us e b o t h p r o c e s s o rs a r e a v a i la b l e in th e s a me p a c k ag e/p i n co un t. t o acco m p lish this, th e v o l t a g e r e gu la t o r m u s t det e c t w h ich p r o c es s o r is p r es e n t and s e t t h e vid d a c an d l o ad line acco r d in g l y . this can acco m p lish e d usin g th e b o ot s e lect o u t p u t f r o m th e cp u . f i gur e 12 s h o w s h o w this sig n al is us ed t o m o dif y th e lo ad lin e and s e t the cp uid p i n o f the ad p 3181 a p p r o p r i a t e l y . t o deter m i n e t h e val u es o f x a n d y , s t a r t w i t h t h e tw o lo ad li n e s; r ol (smal l er s l o p e) an d r oh ( l ar ge r sl op e ) . f i r s t , f o l l ow t h e st anda r d desig n p r o c e d ur e, w h i c h g i ves t h e va lues fo r r cs 1 , r cs 2 , an d c cs fo r r ol . t u n e r ph an d c cs . n e xt, co m p u t e t h e v a l u es fo r r cs 3 and c cs 3 usin g t h e fol l o w ing: cs ol oh cs3 r r r r ? ? ? ? ? ? ? ? ? = 1 ( 3 4 ) ? ? ? ? ? ? ? ? ? = 1 ol oh cs cs3 r r c c ( 3 5 ) w h er e r ol is 1.5 m? an d r oh is 3 m?. 04796-0-010 r ph1 124k ? 19 15 18 17 16 23 22 21 20 adp3181 5vsb to phase inductors c cs1 2.2nf c cs2 1.5nf r cs1 35.7k ? r ph3 124k ? 10k ? 10k ? 2.7k ? 2n3905 bss84 2n3904 2n7001 r cs2 73.2k ? r cs3 c cs3 51 ? r ph2 124k ? r th 100k ? , 5% bootselect cpu nwd hi cpu psc hi to apd3181 cpuid (pin 6) 100nf 100nf 100nf 10k ? sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit f i gure 12. con n ec ti ons to a l low auto mat i c s w itc h ing b e t w een vr 9 and vr 10 o p er ati o n
adp3181 rev. 0 | page 23 of 24 layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for good results, at least a 4-layer pcb is recommended. this should allow the needed ve rsatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mw at room temperature. whenever high currents must be routed between pcb layers, use vias liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the adp3181) must cross through the power circuitry, it is best if a signal ground plane is interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making the signal ground a bit noisier. an analog ground plane should be used around and under the adp3181 for referencing the components associated with the controller. this plane should be tied to the nearest output de- coupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. the components around the adp3181 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb and cssum pins. the output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for example, a microprocessor core). if the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop as described next. power circuitry the switching power path should be routed on the pcb to encompass the shortest possible length to minimize radiated switching noise energy (emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets including all interconnecting pcb traces and planes. the use of short and wide interconnection traces is especially critical in this path because it minimizes the inductance in the switching loop, which can cause high energy ringing, and because it accommodates the high current demand with minimal voltage loss. whenever a power-dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately sur- rounding it, is recommended. two important reasons for this are improved current rating through the vias, and improved thermal perform-ance from vias extended to the opposite side of the pcb where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heat sink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improve thermal performance, use the largest possible pad area. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. signal circuitry the output voltage is sensed and regulated between the fb pin and the fbrtn pin (which connects to the signal ground at the load). to avoid differential mode noise pickup in the sensed signal, the loop area should be small. thus the fb and fbrtn traces should be routed adjacent to each other atop the power ground plane back to the controller. connect the feedback traces from the switch nodes as close as possible to the inductor. the cs ref signal should be connected to the output voltage at the nearest inductor to the controller.
adp3181 rev. 0 | page 24 of 24 outline dimensions 28 15 14 1 8 0 compliant to jedec standards mo-153ae seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 f i gure 13. 2 8 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 28) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ptio n package option quantity per r eel adp3181jruz-reel 1 0c to +85c thin shrink so13 reel ru-28 2500 1 z = pb-fre e part. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04796-0-5/04(0)

▲Up To Search▲

Price & Availability of ADP31810001C

	To Download ADP31810001C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .